| CPC H10D 84/907 (2025.01) [G06F 30/392 (2020.01); H10D 84/854 (2025.01); H10D 89/10 (2025.01); G06F 2119/06 (2020.01); H10D 84/853 (2025.01); H10D 84/961 (2025.01); H10D 84/991 (2025.01)] | 20 Claims |
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1. An integrated circuit (IC) device, comprising:
a plurality of first doped regions of a first semiconductor type over at least one first well region of the first semiconductor type; and
a second doped region of a second semiconductor type over a second well region of the second semiconductor type, the second semiconductor type different from the first semiconductor type,
wherein
the plurality of first doped regions is arranged along a first direction,
each of the plurality of first doped regions has a first length in the first direction,
the second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length,
the plurality of first doped regions is configured to receive a first power supply voltage,
the second doped region is configured to receive a second power supply voltage different from the first power supply voltage,
the plurality of first doped regions is arranged in at least two columns which are adjacent each other in the first direction and elongated in a second direction transverse to the first direction, and
each column of the at least two columns includes multiple first doped regions among the plurality of first doped regions, wherein two immediately adjacent first doped regions among the multiple first doped regions in the column are separated from each other, in the second direction, by a region containing dopants of the second semiconductor type.
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