US 12,408,426 B2
Circuits designed and manufactured with first and second design rules
Chung-Hui Chen, Hsinchu (TW); Tzu-Ching Chang, Dali (TW); Weichih Chen, Hsinchu (TW); Wan-Te Chen, Danshui Township (TW); Tsung-Hsin Yu, Hsinchu (TW); and Cheng-Hsiang Hsieh, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 3, 2021, as Appl. No. 17/542,014.
Claims priority of provisional application 63/163,982, filed on Mar. 22, 2021.
Claims priority of provisional application 63/154,294, filed on Feb. 26, 2021.
Prior Publication US 2022/0278099 A1, Sep. 1, 2022
Int. Cl. G06F 30/30 (2020.01); G06F 30/327 (2020.01); G06F 30/36 (2020.01); G06F 30/392 (2020.01); H10D 84/85 (2025.01); G06F 115/06 (2020.01); G06F 117/12 (2020.01)
CPC H10D 84/853 (2025.01) [G06F 30/327 (2020.01); G06F 30/36 (2020.01); G06F 30/392 (2020.01); G06F 2115/06 (2020.01); G06F 2117/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first plurality of finfets, each finfet of the first plurality of finfets having a first finfet height and at least three fins with adjacent fins of the at least three fins separated by a first distance;
a second plurality of finfets, each finfet of the second plurality of finfets having a second finfet height that is less than the first finfet height and having a first set of two fins separated from each other by a second distance and a second set of two fins separated from each other by the second distance, wherein the first set of two fins is separated from the second set of two fins by a third distance that is greater than the second distance;
a first metal track situated between the first set of two fins and the second set of two fins without being over any part of a fin of the first set of two fins and the second set of two fins;
a second metal track situated over at least part of each of the two fins in the first set of two fins;
a third metal track situated over at least part of each of the two fins in the second set of two fins;
analog circuits that include first finfets of the second plurality of finfets; and
digital circuits that include second finfets of the second plurality of finfets,
wherein the first finfets of the second plurality of finfets directly abut the second finfets of the second plurality of finfets, and
wherein the analog circuits and the digital circuits include a fourth metal track in one direction and a fifth metal track in another direction, wherein the fifth metal track includes a first track segment of the fifth metal track not electrically connected to a second track segment of the fifth metal track to increase maximum electromigration currents in the integrated circuit.