US 12,408,424 B2
Integrated circuit device including an N-channel metal-oxide semiconductor (NMOS) transistor region and a P-channel metal-oxide semiconductor (PMOS) transistor region
Junggil Yang, Hwaseong-si (KR); Minju Kim, Hwaseong-si (KR); and Donghyi Koh, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 18, 2024, as Appl. No. 18/746,928.
Application 18/746,928 is a continuation of application No. 18/212,304, filed on Jun. 21, 2023, granted, now 12,040,326.
Application 18/212,304 is a continuation of application No. 17/372,896, filed on Jul. 12, 2021, granted, now 11,710,739, issued on Jul. 5, 2023.
Claims priority of application No. 10-2020-0166965 (KR), filed on Dec. 2, 2020.
Prior Publication US 2024/0339450 A1, Oct. 10, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/83 (2025.01); H10D 30/62 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 30/6211 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a substrate including a first device region and a second device region;
at least one first channel region extending in a first horizontal direction on the first device region;
at least one second channel region extending in the first horizontal direction on the second device region;
an isolation film covering opposite side walls of each of the at least one first channel region and the at least one second channel region;
a first gate cut insulating pattern on the isolation film on the first device region;
a second gate cut insulating pattern on the isolation film on the second device region;
a gate line extending on the first device region and the second device region in a second horizontal direction that crosses the first horizontal direction, the gate line having a length in the second horizontal direction limited by the first gate cut insulating pattern and the second gate cut insulating pattern, each of the at least one first channel region and the at least one second channel region being surrounded by the gate line; and
an inter-region insulating pattern on the isolation film between the at least one first channel region and the at least one second channel region, the inter-region insulating pattern partially penetrating the gate line in a vertical direction,
wherein the inter-region insulating pattern has a sidewall linearly extended in the vertical direction without a stepped portion.