US 12,408,422 B2
Integrated circuit structures with backside gate cut or trench contact cut
Leonard P. Guler, Hillsboro, OR (US); Charles H. Wallace, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 7, 2021, as Appl. No. 17/340,540.
Prior Publication US 2022/0392896 A1, Dec. 8, 2022
Int. Cl. H10D 84/83 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01)
CPC H10D 84/834 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 62/119 (2025.01); H10D 30/6219 (2025.01)] 10 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first sub-fin structure beneath a first stack of nanowires;
a second sub-fin structure beneath a second stack of nanowires;
a first gate electrode around the first stack of nanowires;
a second gate electrode around the second stack of nanowires; and
a dielectric structure between the first gate electrode and the second gate electrode, wherein the dielectric structure is continuous along an entirety of a height of the first gate electrode and the first sub-fin structure, and wherein the dielectric structure has a bottommost surface at a same level as a bottommost surface of the first sub-fin structure in a cross-sectional view.