| CPC H10D 84/811 (2025.01) [H10D 1/692 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/017 (2025.01)] | 20 Claims |
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1. A device comprising:
a first dielectric layer over a semiconductor substrate;
a second dielectric layer over the first dielectric layer;
a transistor over a first region of the semiconductor substrate, wherein the transistor comprises:
a gate stack in the first dielectric layer, wherein the gate stack comprises a layer of gate dielectric material and a layer of gate electrode material; and
a gate contact in the second dielectric layer, wherein the gate contact physically contacts a top surface of the gate stack, wherein the gate contact comprises a gate contact material; and
a capacitor structure over a second region of the semiconductor substrate, wherein the capacitor structure comprises:
a first electrode and a second electrode in the first dielectric layer, wherein the first electrode and the second electrode comprise the gate electrode material;
a plurality of first electrode contacts in the second dielectric layer, wherein the first electrode contacts physically contact a top surface of the first electrode, wherein the first electrode contacts comprise the gate contact material; and
a plurality of second electrode contacts in the second dielectric layer, wherein the second electrode contacts physically contact a top surface of the second electrode, wherein the second electrode contacts comprise the gate contact material, wherein each first electrode contact on the first electrode is adjacent to at least one corresponding second electrode contact on the second electrode, wherein a second electrode contact corresponding to a first electrode contact is a second electrode contact that is closest to that first electrode contact.
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