| CPC H10D 84/615 (2025.01) [H10D 1/47 (2025.01); H10D 12/038 (2025.01); H10D 12/481 (2025.01)] | 8 Claims |
|
1. A semiconductor device comprising:
a semiconductor substrate having a first region, a second region, and a third region, the second and third regions being surrounded by the first region in a plan view;
a p type semiconductor layer formed on a lower surface of the semiconductor substrate;
an annular first insulating film formed on an upper surface of the semiconductor substrate in the first region to surround the second region and the third region in a plan view;
a trench formed in the upper surface of the semiconductor substrate in the third region;
a gate electrode formed in the trench via a second insulating film in the third region;
a p type semiconductor region formed in the semiconductor substrate in the second region;
a resistor element formed over the p type semiconductor region on the semiconductor substrate via a third insulating film in the second region, the resistor element being electrically connected to the gate electrode;
an interlayer insulating film placed on the resistor element in the second region and on the semiconductor substrate in the third region;
a first plug penetrating from an upper surface of the interlayer insulating film to a lower surface of the interlayer insulating film and formed on an upper surface of the resistor element in the second region;
a second plug penetrating from the upper surface of the interlayer insulating film to the lower surface of the interlayer insulating film and placed on an upper surface of the gate electrode in the third region, wherein a bottom surface of the second plug covers the upper surface of the gate electrode so that the bottom surface of the second plug and the upper surface of the gate electrode are respectively separated from the upper surface of the semiconductor substrate and the interlayer insulating film while the interlayer insulating film is placed directly above a corner between the semiconductor substrate and an upper end of the trench; and
a wiring formed on the resistor element in the second region,
wherein the gate electrode and the resistor element are separated from each other,
wherein the gate electrode and the resistor element are electrically connected to each other via the first plug, the second plug, and the wiring,
wherein the gate electrode and the p type semiconductor layer constitute an IGBT, and
wherein a film thickness of the third insulating film is smaller than a film thickness of the first insulating film and is larger than a film thickness of the second insulating film.
|