US 12,408,416 B2
Silicon carbide semiconductor device and method of manufacturing a silicon carbide semiconductor device
Masaki Miyazato, Matsumoto (JP); and Makoto Utsumi, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed by FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed on Dec. 30, 2021, as Appl. No. 17/566,456.
Claims priority of application No. 2021-018623 (JP), filed on Feb. 8, 2021.
Prior Publication US 2022/0254916 A1, Aug. 11, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 21/66 (2006.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01); H10D 84/00 (2025.01)
CPC H10D 84/144 (2025.01) [H01L 22/14 (2013.01); H10D 12/031 (2025.01); H10D 30/668 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A silicon carbide semiconductor device having a back surface and a lateral surface that forms a chip cross section, the silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first surface and a second surface that are opposite to each other and are parallel to the back surface of the silicon carbide semiconductor device;
a first semiconductor layer of a first conductivity type, provided on the first surface of the silicon carbide substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the first semiconductor layer facing the silicon carbide substrate;
a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer;
a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer, the first semiconductor region having an impurity concentration higher than an impurity concentration of the silicon carbide substrate;
a gate insulating film having a first surface and a second surface opposite to each other, the second surface of the gate insulating film being in contact with the second semiconductor layer;
a gate electrode provided on the first surface of the gate insulating film;
a first electrode provided on surfaces of the second semiconductor layer and the first semiconductor region; and
a second electrode provided on the second surface of the silicon carbide substrate, wherein
the back surface of the silicon carbide semiconductor device has a first region within 30 μm of the lateral surface of the silicon carbide semiconductor device and a second region other than the first region, and
at the back surface of the silicon carbide semiconductor device, the first and second regions have a surface roughness Rp greater than zero, the first region is free of any surface roughness Rp exceeding 4 μm, and the second region is free of any surface roughness Rp exceeding 2 μm, the back surface of the silicon carbide semiconductor device being a back surface of the second electrode.