| CPC H10D 64/691 (2025.01) [H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10D 30/681 (2025.01); H10D 30/69 (2025.01)] | 20 Claims |

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1. Memory circuitry comprising strings of memory cells, comprising:
a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings extending through the insulative tiers and the conductive tiers;
a charge-passage material in the conductive tiers laterally-outward of the channel-material strings;
a storage material in the conductive tiers laterally-outward of the charge-passage material, the storage material extending an entirety of a vertical height of each of the conductive tiers;
a metal oxide consisting of at least one of AlOq, ZrOq, and HfOq in the conductive tiers laterally-outward of the storage material, the metal oxide having upper and lower surfaces in direct physical contact with an insulative material of the insulative tiers;
MoMz in the conductive tiers laterally-outward of the at least one of AlOq, ZrOq, and HfOq, where “M” is at least one of Tc, Bh, Fe, Os, and Hs; “z” being greater than 0 and less than 1.0;
a metal material in the conductive tiers laterally-outward of the MoMz; and
memory cells in individual of the conductive tiers, the memory cells individually comprising:
a channel material of individual of the channel-material strings;
the storage material;
the metal oxide;
the MoMz; and
the metal material.
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