US 12,408,413 B2
Semiconductor device, ferroelectric capacitor and laminated structure
Ying-Chih Chen, Hsinchu (TW); and Blanka Magyari-Kope, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jun. 18, 2024, as Appl. No. 18/747,379.
Application 18/747,379 is a continuation of application No. 18/192,681, filed on Mar. 30, 2023, granted, now 12,040,377.
Application 18/192,681 is a continuation of application No. 17/160,013, filed on Jan. 27, 2021, granted, now 11,621,337, issued on Apr. 4, 2023.
Prior Publication US 2024/0339519 A1, Oct. 10, 2024
Int. Cl. H10D 64/68 (2025.01); H10D 1/68 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01)
CPC H10D 64/685 (2025.01) [H10D 1/682 (2025.01); H10D 1/692 (2025.01); H10D 1/696 (2025.01); H10D 30/701 (2025.01); H10D 64/033 (2025.01); H10D 64/689 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a gate stack including:
a metal gate electrode;
a ferroelectric layer, wherein the ferroelectric layer includes a ferroelectric material including HfSiOx, HfZrOx, Al2O3, TiO2, LaOx, BaSrTiOx (BST), PbZrxTiyOz (PZT), BiFeO3 (BFO) or (PbyLaw)(ZrxTiy)Oz (PLZT), or a combination thereof;
a semiconducting oxide layer disposed between the ferroelectric layer and the metal gate electrode, wherein the semiconducting oxide layer has a thickness between approximately 1 μm and approximately 30 μm; and
a channel layer over the gate stack.