US 12,408,412 B2
Air spacers around contact plugs and method forming same
Chen-Huang Huang, Hsinchu (TW); Ming-Jhe Sie, Taipei (TW); Yih-Ann Lin, Jhudong Township (TW); An Chyi Wei, Hsinchu (TW); and Ryan Chia-Jen Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 8, 2024, as Appl. No. 18/658,521.
Application 18/658,521 is a continuation of application No. 17/805,552, filed on Jun. 6, 2022, granted, now 12,015,071.
Application 17/805,552 is a continuation of application No. 16/806,280, filed on Mar. 2, 2020, granted, now 11,355,616, issued on Jun. 7, 2022.
Claims priority of provisional application 62/928,746, filed on Oct. 31, 2019.
Prior Publication US 2024/0297235 A1, Sep. 5, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 64/66 (2025.01); H01L 21/285 (2006.01); H01L 21/3213 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/62 (2025.01); H10D 84/01 (2025.01)
CPC H10D 64/679 (2025.01) [H01L 21/28518 (2013.01); H01L 21/764 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a transistor comprising:
a semiconductor region;
a gate stack on the semiconductor region;
a source/drain region aside of the gate stack; and
a silicide region over the source/drain region;
a first inter-layer dielectric over the source/drain region, wherein the gate stack is in the first inter-layer dielectric;
a contact plug electrically connecting to the transistor, wherein the contact plug comprises a part in the first inter-layer dielectric; and
an air spacer comprising a first portion in the first inter-layer dielectric, and a second portion higher than the first inter-layer dielectric.