US 12,408,411 B2
Semiconductor device
Chang-Yin Chen, Taipei (TW); Che-Cheng Chang, New Taipei (TW); and Chih-Han Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Feb. 5, 2024, as Appl. No. 18/432,694.
Application 16/914,940 is a division of application No. 16/047,038, filed on Jul. 27, 2018, granted, now 10,700,180, issued on Jun. 30, 2020.
Application 18/432,694 is a continuation of application No. 17/129,253, filed on Dec. 21, 2020, granted, now 11,929,419.
Application 17/129,253 is a continuation of application No. 16/914,940, filed on Jun. 29, 2020, granted, now 10,872,965, issued on Dec. 22, 2020.
Prior Publication US 2024/0178300 A1, May 30, 2024
Int. Cl. H10D 64/66 (2025.01); H01L 21/28 (2025.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/033 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/762 (2006.01)
CPC H10D 64/679 (2025.01) [H01L 21/28088 (2013.01); H10D 30/024 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H01L 21/0206 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02236 (2013.01); H01L 21/02255 (2013.01); H01L 21/02271 (2013.01); H01L 21/02274 (2013.01); H01L 21/0274 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/3212 (2013.01); H01L 21/76224 (2013.01); H10D 64/667 (2025.01)] 20 Claims
OG exemplary drawing
 
11. A device, comprising:
a semiconductor fin extending from a substrate;
a gate structure extending across the semiconductor fin; and
a multilayer gate spacer abutting a sidewall of the gate structure, the multilayer gate spacer comprising:
a first spacer layer in contact with the sidewall of the gate structure;
a second spacer layer in contact with a sidewall of the first spacer layer oriented away from the gate structure;
a third spacer layer in contact with a sidewall of the second spacer layer oriented away from the second spacer layer; and
an air-filled region atop the third spacer layer;
a source/drain region over the semiconductor fin; and
a contact etch stop layer over the source/drain region, wherein the contact etch stop layer defines a vertical boundary of the air-filled region, and the contact etch stop layer has a top end not lower than a top end of the first spacer layer.