US 12,408,409 B2
Semiconductor structure and forming method thereof
Tzung-Han Lee, Hefei (CN); and Chun-Wei Liao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 10, 2023, as Appl. No. 18/152,205.
Application 18/152,205 is a continuation of application No. PCT/CN2022/074554, filed on Jan. 28, 2022.
Claims priority of application No. 202110790428.0 (CN), filed on Jul. 13, 2021.
Prior Publication US 2023/0163179 A1, May 25, 2023
Int. Cl. H10D 62/13 (2025.01); H01L 21/265 (2006.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01)
CPC H10D 64/258 (2025.01) [H01L 21/26513 (2013.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a gate structure, wherein the gate structure is located on the substrate;
a plurality of doped regions, located in the substrate, and located at two sides of the gate structure, wherein
one of the plurality of doped regions comprises a first doped region and a second doped region, a concentration of doped ions in the first doped region is greater than a concentration of doped ions in the second doped region, and the first doped region is farther from a sidewall of the gate structure than the second doped region;
an electrical contact layer, wherein the electrical contact layer is in contact with a sidewall of the first doped region far from the gate structure, and a top surface of the electrical contact layer is higher than a surface of the substrate; and
a dielectric layer, wherein the dielectric layer fills a space between the electrical contact layer and the gate structure.