CPC H10D 64/254 (2025.01) [H01L 23/3171 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 24/16 (2013.01); H10D 64/258 (2025.01); H01L 2224/16227 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/30101 (2013.01); H01L 2924/3011 (2013.01)] | 6 Claims |
1. A metal oxide semiconductor (MOS) with multiple drain vias, comprising:
a semiconductor substrate, having a gate region, a source region and a drain region, wherein, the gate region, the source region, and the drain region each has a respective connection layer made of a metal material and formed on a same surface of the semiconductor substrate;
the semiconductor substrate having an epitaxy layer with a slot formed through the epitaxy layer, wherein a first protective layer fills the slot;
a plurality of vias extending into the semiconductor substrate in the drain region, extending through the first protective layer and the epitaxy layer, and being filled with the connection layer;
a second protective layer formed on the connection layers of the gate region, the source region and the drain region; and
a plurality of contact vias formed through the second protective layer;
wherein, the connection layers being coplanar to each other on the gate region, on the source region and on the drain region are insulated and separated from each other by the second protective layer, and are each electrically connected to a respective conductive element in the contact via; and
the MOS is electrically connected to the outside through the conductive elements on the same surface.
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