US 12,408,406 B2
Semiconductor device and manufacturing method thereof
Lin-Yu Huang, Hsinchu (TW); and Po-Chin Chang, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 13, 2022, as Appl. No. 17/864,372.
Prior Publication US 2024/0021673 A1, Jan. 18, 2024
Int. Cl. H10D 64/23 (2025.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01)
CPC H10D 64/254 (2025.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10D 30/0198 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
two source/drain features, laterally arranged to each other;
one or more channel layers, connecting the two source/drain features;
a gate structure, engaging the one or more channel layers and interposing the two source/drain features;
a first contact plug, extending from above a first source/drain feature of the two source/drain features to the first source/drain feature;
a second contact plug, extending from below a second source/drain feature of the two source/drain features to the second source/drain feature;
a conductive line, disposed underneath the second contact plug and electrically coupled to the second contact plug; and
a nitride capping layer, disposed between the second contact plug and the conductive line, wherein sidewalls of the conductive line are free of the nitride capping layer.