US 12,408,405 B2
Device comprising spacers including a localised airgap and associated manufacturing methods
Fabrice Nemouchi, Grenoble (FR); Cyrille Le Royer, Grenoble (FR); and Nicolas Posseme, Grenoble (FR)
Assigned to COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed by COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed on Oct. 14, 2022, as Appl. No. 17/966,217.
Claims priority of application No. 2110869 (FR), filed on Oct. 14, 2021.
Prior Publication US 2023/0120901 A1, Apr. 20, 2023
Int. Cl. H10D 64/01 (2025.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01)
CPC H10D 64/021 (2025.01) [H10D 62/115 (2025.01); H10D 64/01 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H01L 21/76283 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device made on a substrate comprising at least one active region and at least one non-active region at least partially surrounding the at least one active region,
a plurality of gate stacks, a part of each gate stack of the plurality of gate stacks being on the at least one active region and a part of said plurality of gate stacks being on the at least one non-active region,
each gate stack being separated from at least one of the adjacent gate stacks by a spacer formed of a spacer material by a distance equal to e,
wherein, for each gate stack of the plurality of gate stacks, the part of the gate stack located on the at least one active region has a height h2, the part of the same gate stack located on the at least one non-active region has a height h1, and wherein h2/e=a2 and h1/e=a1
where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in said spacer,
and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in said spacer.