US 12,408,403 B2
Field effect transistor with stacked unit subcell structure
Kyle Bothe, Cary, NC (US); Jia Guo, New Hill, NC (US); Yueying Liu, Cary, NC (US); Jeremy Fisher, Raleigh, NC (US); and Scott T. Sheppard, Chapel Hill, NC (US)
Assigned to MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Jun. 24, 2022, as Appl. No. 17/848,984.
Application 17/848,984 is a continuation in part of application No. 17/325,576, filed on May 20, 2021, granted, now 11,658,234.
Application 17/325,576 is a continuation in part of application No. 17/081,476, filed on Oct. 27, 2020, granted, now 11,502,178.
Prior Publication US 2022/0328634 A1, Oct. 13, 2022
Int. Cl. H10D 62/85 (2025.01); H10D 30/47 (2025.01); H10D 62/13 (2025.01); H10D 64/00 (2025.01); H10D 64/27 (2025.01)
CPC H10D 62/8503 (2025.01) [H10D 30/475 (2025.01); H10D 62/149 (2025.01); H10D 64/111 (2025.01); H10D 64/112 (2025.01); H10D 64/411 (2025.01); H10D 64/518 (2025.01)] 31 Claims
OG exemplary drawing
 
26. A gallium nitride based transistor device, comprising:
a plurality of pairs of unit subcells, the unit subcells of each pair of unit subcells having gate fingers aligned in a first direction, wherein the plurality of pairs of unit subcells are spaced apart in a second direction that is perpendicular to the first direction;
wherein each of the unit subcells of the transistor device has a gate finger width less than 200 microns; and
wherein the transistor device is capable of achieving a linear power density relative to the second direction of greater than 40 W/mm at an operating frequency of 10 GHZ, wherein each pair of unit subcells comprises:
a first unit subcell comprising:
a first active region having a first active region width extending in the first direction;
a first source contact in the first active region extending in the first direction;
a drain contact in the first active region and extending in the first direction, the first source contact and the drain contact defining a first channel region in the first active region between the first source contact and the drain contact, the first channel region configured to permit current flow between the first source contact and the drain contact in the second direction, wherein the drain contact extends outside the active region; and
a first gate finger between the first source contact and the drain contact, wherein the first gate finger extends in the first direction and is configured to modulate a conductivity of the first channel region in response to a gate voltage; and
a second unit subcell arranged adjacent the first unit subcell in the first direction, the second unit subcell comprising:
a second active region having a second active region width extending in the first direction, wherein the drain contact extends into the second active region;
a second source contact in the second active region and extending in the first direction, the second source contact and the drain contact defining a second channel region in the second active region between the second source contact and the drain contact, the second channel region configured to permit current flow between the second source contact and the drain contact in the second direction;
a second gate finger between the second source contact and the drain contact, wherein the second gate finger extends in the first direction and is configured to modulate a conductivity of the second channel region in response to the gate voltage; and
a first field plate in the first channel region, wherein the first field plate is connected to the first source contact outside the first active region without crossing over the first gate finger.