US 12,408,399 B2
Semiconductor device including two-dimensional semiconductor material
Minhyun Lee, Suwon-si (KR); Minsu Seol, Suwon-si (KR); Yeonchoo Cho, Seongnam-si (KR); and Hyeonjin Shin, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 2, 2024, as Appl. No. 18/761,779.
Application 18/761,779 is a division of application No. 18/055,565, filed on Nov. 15, 2022, granted, now 12,062,697.
Application 18/055,565 is a continuation of application No. 16/928,508, filed on Jul. 14, 2020, granted, now 11,508,815, issued on Nov. 22, 2022.
Claims priority of application No. 10-2020-0007964 (KR), filed on Jan. 21, 2020.
Prior Publication US 2024/0363689 A1, Oct. 31, 2024
Int. Cl. H01L 29/10 (2006.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01); H10D 64/27 (2025.01)
CPC H10D 62/292 (2025.01) [H01L 21/02568 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 64/118 (2025.01); H10D 64/514 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a plurality of gate electrodes on the substrate, each of the plurality of gate electrodes having a shape with a height greater than a width;
a connection electrode on the substrate, the connection electrode connecting the plurality of gate electrodes to each other;
a plurality of gate dielectrics on the plurality of gate electrodes;
a plurality of channel layers on the plurality of gate dielectrics, the plurality of channel layers comprising a two-dimensional semiconductor material; and
a source electrode and a drain electrode that are electrically connected to the plurality of channel layers.