| CPC H10D 62/177 (2025.01) [H10D 8/00 (2025.01); H10D 12/038 (2025.01); H10D 12/481 (2025.01)] | 4 Claims |
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1. A power semiconductor device, comprising a collector located at the bottom, a heavily doped first conductivity type cathode region and a heavily doped second conductivity type collector region arranged on the collector in a staggered manner, a first conductivity type buffer layer located on the heavily doped first conductivity type cathode region and a heavily doped collector region, a first conductivity type drift region located on the first conductivity type buffer layer, and an emitter electrode located on the top of the device, the emitter electrode is separated from the first conductivity type drift region, wherein more than one frontside structure units are arranged on the first conductivity type drift region, each of the frontside structure units comprises: a trench gate structure, a second conductivity type base region adjacent to the trench gate structure, a lightly doped second conductivity type base region located on one side of the second conductivity type base region to isolate a trench auxiliary gate structure from the second conductivity type base region, the trench auxiliary gate structure, and a floating FP region located at the bottom of the trench auxiliary gate structure; the trench gate structure comprises a first gate dielectric layer and a first gate electrode; the floating FP region is separated from the second conductivity type base region and the lightly doped second conductivity type base region; an upper surface of the second conductivity type base region is provided with a first heavily doped first conductivity type emitter region and a heavily doped second conductivity type emitter region, an upper surface of the lightly doped second conductivity type base region is provided with a second heavily doped first conductivity type emitter region, and the first heavily doped first conductivity type emitter region is separated from the second heavily doped first conductivity type emitter region; an upper surface of the trench gate structure is provided with an insulated dielectric layer for isolating the first gate dielectric layer from the emitter electrode, a second gate electrode is arranged in the trench auxiliary gate structure, the second gate electrode, the heavily doped first conductivity type emitter region and the heavily doped second conductivity type emitter region are connected to one another by means of the emitter electrode, and all frontside structure units are connected to one another by the emitter electrode; the second heavily doped first conductivity type emitter region, the lightly doped second conductivity type base region and the first conductivity type drift region form a punch-through triode structure,
the second conductivity type base region, the first conductivity type drift region and the floating FP region form a JFET structure;
the second conductivity type base region and the floating FP region have the same doping dose, and the second conductivity type base region and the floating FP region form a Schottky contact with the emitter electrode;
the second gate electrode is formed by the emitter electrode filled in the trench, and an upper surface of the floating FP region is directly connected to the emitter electrode at the bottom of the trench auxiliary gate structure; and
the topography of the trench gate structure and the trench auxiliary gate structure is inverted trapezoidal, the lightly doped second conductivity type base region and the second heavily doped first conductivity type emitter region on the surface thereof are both located on left and right sidewalls of the trench auxiliary gate structure.
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