US 12,408,396 B1
Field-effect transistors with heterogenous doped regions in the substrate of a silicon-on-insulator substrate
Richard Taylor, III, Campbell, CA (US); and Andreas Knorr, Saratoga Springs, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Aug. 23, 2024, as Appl. No. 18/814,235.
Int. Cl. H10D 86/00 (2025.01); H10D 62/13 (2025.01); H10D 64/23 (2025.01)
CPC H10D 62/151 (2025.01) [H10D 64/256 (2025.01); H10D 86/201 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a silicon-on-insulator substrate including a semiconductor layer, a semiconductor substrate, and a dielectric layer between the semiconductor layer and the semiconductor substrate, the semiconductor substrate including a first doped region and a second doped region, the first doped region having a first conductivity type, and the second doped region having a second conductivity type different from the first conductivity type;
a first source/drain region in the semiconductor layer, the first source/drain region overlapping with the first doped region;
a second source/drain region in the semiconductor layer, the second source/drain region overlapping with the second doped region; and
a first gate structure laterally between the first source/drain region and the second source/drain region,
wherein the semiconductor substrate includes a third doped region having the second conductivity type, the first doped region is laterally positioned between the second doped region and the third doped region, the first gate structure has a width, and the second doped region is laterally spaced from the third doped region by a distance greater than two times the width of the first gate structure.