US 12,408,395 B2
Semiconductor device having high driving capability and steep subthreshold swing (SS) characteristic and method of manufacturing the same
Yongliang Li, Beijing (CN); Xiaohong Cheng, Beijing (CN); Fei Zhao, Beijing (CN); Jun Luo, Beijing (CN); and Wenwu Wang, Beijing (CN)
Assigned to INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Filed by INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Filed on Nov. 29, 2022, as Appl. No. 18/059,960.
Claims priority of application No. 202210131205.8 (CN), filed on Feb. 11, 2022.
Prior Publication US 2023/0261050 A1, Aug. 17, 2023
Int. Cl. H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/60 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/0243 (2025.01); H10D 30/43 (2025.01); H10D 30/611 (2025.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate; and
a channel portion, comprising:
a first portion comprising a fin-shaped structure protruding with respect to the substrate;
a second portion located above the first portion and spaced apart from the first portion, wherein the second portion comprises one or more nanowires or nanosheets spaced apart from each other;
source/drain portions arranged on two opposite sides of the channel portion in a first direction and being in contact with the channel portion; and
a gate stack extending on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion
wherein the gate stack comprises:
a first portion intersecting with the first portion of the channel portion; and
a second portion intersecting with the second portion of the channel portion;
wherein the first portion of the gate stack comprises a first gate dielectric layer and a first gate metal layer;
wherein the second portion of the gate stack comprises a second gate dielectric layer and a second gate metal layer; and
wherein the first gate dielectric layer is different from the second gate dielectric layer and/or the first gate metal layer is different from the second gate metal layer.