| CPC H10D 62/118 (2025.01) [H01L 21/28518 (2013.01); H01L 21/31111 (2013.01); H10D 30/6735 (2025.01)] | 20 Claims |

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1. A method for forming a semiconductor device structure, comprising:
forming nanostructures over a front side of a substrate;
forming a gate structure surrounding the nanostructures;
forming a source/drain structure beside the gate structure;
forming a trench though the substrate from a back side of the substrate;
forming a first silicide layer in contact with the source/drain structure;
forming a second silicide layer over the first silicide layer and sidewalls of the trench;
depositing a first conductive material over the second silicide layer;
etching back the first conductive material;
etching back the second silicide layer; and
depositing a second conductive material in the trench.
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