| CPC H10D 62/115 (2025.01) [H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 84/83 (2025.01); H10D 30/014 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01)] | 15 Claims |
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1. A semiconductor device comprising:
a substrate comprising an active region extending in a first direction;
a gate electrode extending in a second direction and intersecting the active region on the substrate, the gate electrode comprising at least one first electrode layer and a second electrode layer;
a plurality of channel layers on the active region and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, the plurality of channel layers at least partially surrounded by the gate electrode;
a plurality of source/drain regions, with at least one source/drain region on each side of the gate electrode, the plurality of source/drain regions electrically connected to the plurality of channel layers; and
one or more air gap regions in the second electrode layer between respective ones of the plurality of channel layers and between a lowermost channel layer of the plurality of channel layers and the active region in the third direction,
wherein the at least one first electrode layer or the second electrode layer has a first thickness between adjacent ones of the plurality of channel layers in the third direction, and has a second thickness on side surfaces of the plurality of channel layers, and wherein the second thickness is greater than the first thickness.
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