US 12,408,389 B2
Semiconductor device and method for forming the same
Kuan-Ting Chen, Taichung (TW); Shu-Tong Chang, Taoyuan (TW); and Min-Hung Lee, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); NATIONAL TAIWAN UNIVERSITY, Taipei (TW); and NATIONAL TAIWAN NORMAL UNIVERSITY, Taipei (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); NATIONAL TAIWAN UNIVERSITY, Taipei (TW); and National Taiwan Normal University, Taipei (TW)
Filed on Jun. 28, 2024, as Appl. No. 18/759,212.
Application 17/874,005 is a division of application No. 17/110,536, filed on Dec. 3, 2020, granted, now 11,942,546, issued on Mar. 26, 2024.
Application 18/759,212 is a continuation of application No. 17/874,005, filed on Jul. 26, 2022, granted, now 12,062,719.
Prior Publication US 2024/0355926 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/69 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01)
CPC H10D 30/701 (2025.01) [H01L 21/02181 (2013.01); H01L 21/02189 (2013.01); H01L 21/02205 (2013.01); H01L 21/0228 (2013.01); H10D 30/0415 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a semiconductor layer over the substrate;
a gate structure wrapping around the semiconductor layer, wherein the gate structure comprises:
an interfacial layer;
a quasi-antiferroelectric (QAFE) layer over the interfacial layer, and wherein in a polarization-voltage curve of the QAFE layer, when a sweeping voltage of 3V is applied, a remnant polarization (Pr) of the QAFE layer is in a range from about 0.5 μC/cm2 to about 5 μC/cm2 and a coercive voltage (Vc) of the QAFE layer is in a range from about 0.1 V to about 0.5 V; and
a gate electrode over the QAFE layer;
source/drain regions on opposite sides of the gate structure; and
gate spacers on opposite sidewalls of the gate structure, wherein the QAFE layer has a portion in direct contact with the gate spacers, the portion has a U-shape cross-sectional profile, and a bottom surface of the portion is higher than bottom surfaces of the gate spacers.