| CPC H10D 30/701 (2025.01) [H10D 30/014 (2025.01); H10D 30/015 (2025.01); H10D 30/021 (2025.01); H10D 30/0415 (2025.01); H10D 30/62 (2025.01); H10D 64/689 (2025.01)] | 12 Claims |
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1. An integrated assembly, comprising:
a ferroelectric transistor; the ferroelectric transistor comprising an active region which extends vertically between a first electrode and a second electrode; the active region comprising a first source/drain region proximate the first electrode, a second source/drain region proximate the second electrode, and a body region between the first and second source/drain regions; the ferroelectric transistor including a conductive gate proximate a segment of the body region, said segment being a gated channel region; the active region including a first semiconductor composition extending from a surface of the first electrode, across the first source/drain region and across the gated channel region; the active region including a second semiconductor composition extending from the first semiconductor composition to a surface of the second electrode; the first semiconductor composition comprising a semiconductor oxide, and the second semiconductor composition being compositionally different than the first semiconductor composition;
a first comparative digit line coupled with the first source/drain region; and
a second comparative digit line coupled with the second source/drain region.
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