| CPC H10D 30/6757 (2025.01) [H10D 30/0321 (2025.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/873 (2023.02)] | 18 Claims |
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1. A thin-film transistor substrate comprising:
a substrate;
a buffer layer on the substrate;
a semiconductor layer arranged on a top surface of the buffer layer and comprising a first conductive area, a second conductive area, and a channel area between the first conductive area and the second conductive area;
a first dopant doped in an upper portion of the channel area at a first concentration;
a second dopant doped in a lower portion of the channel area at a second concentration and being of a different type from a type of the first dopant;
a gate insulating layer covering the semiconductor layer;
a gate electrode overlapping the channel area in a plan view and disposed on the gate insulating layer; and
a barrier layer disposed under a bottom surface of the buffer layer,
wherein the first dopant is doped in the barrier layer.
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