US 12,408,384 B2
Semiconductor device and display device including the semiconductor device
Yasutaka Nakazawa, Tochigi (JP); Junichi Koezuka, Tochigi (JP); and Takashi Hamochi, Tochigi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Nov. 20, 2023, as Appl. No. 18/513,803.
Application 18/513,803 is a continuation of application No. 17/346,359, filed on Jun. 14, 2021, granted, now 11,830,950.
Application 17/346,359 is a continuation of application No. 16/888,892, filed on Jun. 1, 2020, granted, now 11,107,930, issued on Aug. 31, 2021.
Application 16/888,892 is a continuation of application No. 16/071,770, granted, now 10,734,529, issued on Aug. 4, 2020, previously published as PCT/IB2017/050230, filed on Jan. 17, 2017.
Claims priority of application No. 2016-015730 (JP), filed on Jan. 29, 2016.
Prior Publication US 2024/0088303 A1, Mar. 14, 2024
Int. Cl. H10D 30/67 (2025.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01); H10D 64/62 (2025.01); H10D 84/08 (2025.01); H10D 84/80 (2025.01); H10D 84/83 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 88/00 (2025.01); H10D 99/00 (2025.01); H10F 39/12 (2025.01); H10H 29/10 (2025.01)
CPC H10D 30/6755 (2025.01) [H01L 21/76843 (2013.01); H01L 21/76856 (2013.01); H10B 12/312 (2023.02); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6734 (2025.01); H10D 30/6757 (2025.01); H10D 64/62 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01); H10D 99/00 (2025.01); H10F 39/12 (2025.01); H10H 29/10 (2025.01); H10D 84/08 (2025.01); H10D 84/811 (2025.01); H10D 84/83 (2025.01); H10D 88/00 (2025.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a first conductive film over the substrate;
a first insulating film over the first conductive film;
a second insulating film over the first insulating film;
an oxide semiconductor film and a second conductive film over the second insulating film;
a third insulating film over the oxide semiconductor film and the second conductive film;
a fourth insulating film over the third insulating film; and
a third conductive film over the fourth insulating film,
wherein the first conductive film is configured to function as a first gate electrode of a transistor,
wherein the third conductive film is configured to function as a second gate electrode of the transistor,
wherein the oxide semiconductor film comprises a channel formation region of the transistor,
wherein the second conductive film comprises a fourth conductive film, a fifth conductive film, and a sixth conductive film,
wherein the fourth conductive film is in contact with the first conductive film in a first opening provided in the first insulating film and the second insulating film,
wherein the third conductive film is in contact with the sixth conductive film in a second opening provided in the third insulating film and the fourth insulating film, and
wherein an end portion of the fifth conductive film comprises copper and silicon.