US 12,408,383 B2
Semiconductor device, semiconductor wafer, and electronic device
Eri Sato, Kanagawa (JP); Tatsuya Onuki, Kanagawa (JP); Yuto Yakubo, Kanagawa (JP); and Hitoshi Kunitake, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed on Jan. 12, 2024, as Appl. No. 18/411,830.
Application 18/411,830 is a continuation of application No. 17/284,553, granted, now 11,935,961, previously published as PCT/IB2019/058754, filed on Oct. 15, 2019.
Claims priority of application No. 2018-196390 (JP), filed on Oct. 18, 2018; and application No. 2019-011578 (JP), filed on Jan. 25, 2019.
Prior Publication US 2024/0154040 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 3/45 (2006.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01)
CPC H10D 30/6755 (2025.01) [H10D 62/80 (2025.01); H10D 30/6732 (2025.01); H10D 30/6745 (2025.01); H10D 30/6746 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a transistor comprising a gate and a metal oxide in a channel formation region; and
an operational amplifier,
wherein an inverting input terminal of the operational amplifier is electrically connected to a first terminal of the transistor and the gate of the transistor,
wherein the operational amplifier is a single-polarity circuit using transistors comprising the metal oxide in channel formation regions,
wherein an output terminal of the operational amplifier is electrically connected to a second terminal of the transistor, and
wherein an off-state current of the transistor is less than or equal to 1.0×10−12 A.