US 12,408,382 B2
Semiconductor memory device having a confinement layer with a two-dimensional electron gas in the confinement layer
Jae Kyeong Jeong, Seoul (KR); Min Tae Ryu, Hwaseong-si (KR); Hyeon Joo Seul, Seoul (KR); Sungwon Yoo, Hwaseong-si (KR); Wonsok Lee, Suwon-si (KR); Min Hee Cho, Suwon-si (KR); and Jae Seok Hur, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR); and IUCF-HYU (Industry-University Cooperation Foundation Hanyang University), Seoul (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 15, 2022, as Appl. No. 17/694,903.
Claims priority of application No. 10-2021-0062532 (KR), filed on May 14, 2021.
Prior Publication US 2022/0367721 A1, Nov. 17, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 23/00 (2006.01); H10B 12/00 (2023.01); H10D 30/47 (2025.01); H10D 30/67 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01)
CPC H10D 30/6755 (2025.01) [H01L 24/08 (2013.01); H10B 12/05 (2023.02); H10B 12/50 (2023.02); H10D 30/475 (2025.01); H10D 30/477 (2025.01); H10D 30/478 (2025.01); H10D 30/6757 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01); H01L 2224/08145 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a bit line extending in a first direction;
a channel pattern on the bit line, the channel pattern including a first oxide semiconductor layer contacting the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, each of the first and second oxide semiconductor layers including a horizontal part parallel to the bit line and a first vertical part and a second vertical part that vertically protrude from the horizontal part;
a first word line and a second word line that are between the first and second vertical parts of the second oxide semiconductor layer and are on the horizontal part of the second oxide semiconductor layer, the first and second word lines running across the bit line; and
a gate dielectric pattern between the channel pattern and the first and second word lines, the gate dielectric pattern on the first and second vertical parts,
wherein a thickness of the second oxide semiconductor layer is greater than a thickness of the first oxide semiconductor layer.