| CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 64/021 (2025.01)] | 20 Claims |
|
1. A semiconductor device, comprising:
a substrate including an active pattern;
a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns vertically stacked to be spaced apart from each other;
a source/drain pattern connected to the plurality of semiconductor patterns;
a gate electrode on the plurality of semiconductor patterns, the gate electrode extending in a first direction that is parallel to a top surface of the substrate; and
a gate insulating layer between the plurality of semiconductor patterns and the gate electrode,
wherein a first semiconductor pattern of the plurality of semiconductor patterns includes opposite side surfaces, which are opposite to each other in the first direction, a bottom surface, and a top surface,
wherein the gate insulating layer covers the opposite side surfaces of the first semiconductor pattern, the bottom surface of the first semiconductor pattern, and the top surface of the first semiconductor pattern,
wherein the gate insulating layer includes
a first region on one of the opposite side surfaces of the first semiconductor pattern; and
a second region on one of the top surface of the first semiconductor pattern or the bottom surface of the first semiconductor pattern, and
wherein a thickness of the first region in the first direction is greater than a thickness of the second region in a second direction that is perpendicular to the top surface of the substrate.
|