| CPC H10D 30/6735 (2025.01) [H10B 12/30 (2023.02); H10B 12/482 (2023.02); H10D 30/031 (2025.01); H10D 30/6757 (2025.01)] | 19 Claims |
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1. A semiconductor structure, comprising:
a base, comprising bit lines and semiconductor channels that are respectively arranged at intervals, wherein a bit line extends in a first direction, a semiconductor channel is located on partial top surface of the bit line, and in a direction perpendicular to the top surface of the bit line, and the semiconductor channel comprises a first region, a second region and a third region arranged in sequence;
a dielectric layer, located between two adjacent ones of the bit lines and on a surface of the semiconductor channel;
a first gate layer, surrounding the dielectric layer of the second region and extending in a second direction, wherein the first direction is different from the second direction;
a second gate layer, surrounding the dielectric layer of the third region, wherein, in the direction perpendicular to the top surface of the bit line, the second gate layer is spaced apart from the first gate layer; and
an insulation layer, located between two adjacent ones of the semiconductor channels on the same bit line and isolating the first gate layers and the second gate layers on two adjacent ones of the dielectric layers;
wherein,
the single first gate layer extends in the second direction, and surrounds two adjacent ones of the semiconductor channels respectively located on two adjacent ones of the bit lines; and
the single second gate layer only surrounds the single semiconductor channel.
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