US 12,408,374 B2
Transistor arrangement with a load transistor and a sense transistor
Gerhard Noebauer, Villach (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jul. 1, 2024, as Appl. No. 18/760,559.
Application 18/093,241 is a division of application No. 17/104,216, filed on Nov. 25, 2020, granted, now 11,575,041, issued on Feb. 7, 2023.
Application 17/104,216 is a division of application No. 16/248,014, filed on Jan. 15, 2019, granted, now 10,872,976, issued on Dec. 22, 2020.
Application 18/760,559 is a continuation of application No. 18/093,241, filed on Jan. 4, 2023, granted, now 12,062,718.
Claims priority of application No. 18151843 (EP), filed on Jan. 16, 2018.
Prior Publication US 2024/0355923 A1, Oct. 24, 2024
Int. Cl. H10D 30/66 (2025.01); G01R 19/00 (2006.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/00 (2025.01)
CPC H10D 30/669 (2025.01) [H10D 30/668 (2025.01); H10D 62/127 (2025.01); H10D 62/154 (2025.01); H10D 62/158 (2025.01); H10D 64/111 (2025.01); H10D 64/117 (2025.01); G01R 19/0092 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A transistor arrangement, comprising:
a drift and drain region arranged in a semiconductor body and each connected to a drain node;
a plurality of load transistor cells each comprising a source region integrated in a first region of the semiconductor body;
a plurality of sense transistor cells each comprising a source region integrated in a second region of the semiconductor body;
a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor; and
a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor; and
wherein a resistance of the second source conductor is different from a resistance of the first source conductor,
wherein the second source conductor comprises:
a second source metallization connected to the source region of each transistor cell of the plurality of sense transistor cells;
a second source pad spaced apart from the second source metallization in a horizontal direction of the semiconductor body; and
a connection line electrically connecting the second source metallization with the second source pad,
wherein the connection line comprises an elongated span with a plurality of meanders,
wherein a direction of the connection line reverses at each meander.