US 12,408,371 B2
NMOS half-bridge power device and manufacturing method thereof
Chih-Wen Hsiung, Hsinchu (TW); Wu-Te Weng, Hsinchu (TW); and Ta-Yung Yang, Taoyuan (TW)
Assigned to RICHTEK TECHNOLOGY CORPORATION, Zhubei (TW)
Filed by Richtek Technology Corporation, HsinChu (TW)
Filed on Nov. 9, 2022, as Appl. No. 17/983,434.
Claims priority of provisional application 63/264,934, filed on Dec. 3, 2021.
Claims priority of application No. 111116926 (TW), filed on May 5, 2022.
Prior Publication US 2023/0178648 A1, Jun. 8, 2023
Int. Cl. H03F 3/217 (2006.01); H02M 3/335 (2006.01); H02M 7/219 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/65 (2025.01); H10D 62/17 (2025.01); H10D 64/27 (2025.01)
CPC H10D 30/65 (2025.01) [H03F 3/2173 (2013.01); H10D 30/0221 (2025.01); H10D 30/603 (2025.01); H10D 62/393 (2025.01); H10D 64/516 (2025.01); H02M 3/33571 (2021.05); H02M 7/219 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An NMOS half-bridge power device, comprising:
a semiconductor layer, which is formed on a substrate;
a plurality of insulation regions, which are formed on the semiconductor layer, for defining an NMOS upper gate device region and an NMOS lower gate device region, wherein an NMOS upper gate device is formed in the NMOS upper gate device region, whereas, an NMOS lower gate device is formed in the NMOS lower gate device region;
a first N-type buried layer, which is formed in the NMOS upper gate device region;
a first N-type high voltage isolation region and a second N-type high voltage isolation region, which are formed in the semiconductor layer of the NMOS upper gate device region by one same ion implantation process;
a first N-type high voltage well and a second N-type high voltage well, which are formed in the semiconductor layer of the NMOS upper gate device region and the semiconductor layer of the NMOS lower gate device region, respectively, by one same ion implantation process;
a first P-type high voltage well and a second P-type high voltage well, which are formed in the semiconductor layer of the NMOS upper gate device region and the semiconductor layer of the NMOS lower gate device region, respectively, by one same ion implantation process; wherein the first N-type high voltage well and the first P-type high voltage well are in contact with each other in a channel direction, and wherein the second N-type high voltage well and the second P-type high voltage well are in contact with each other in the channel direction;
a first drift oxide region and a second drift oxide region, which are formed, by one same etching process including etching a drift oxide layer, in the NMOS upper gate device region and in the NMOS lower gate device region, respectively;
a first gate and a second gate, which are formed, by one same etching process including etching a polysilicon layer, in the NMOS upper gate device region and in the NMOS lower gate device region, respectively;
a first P-type body region and a second P-type body region, which are formed in the semiconductor layer of the NMOS upper gate device region and the semiconductor layer of the NMOS lower gate device region, respectively, by one same ion implantation process; wherein a portion of the first P-type body region is located vertically below the first gate, and wherein the first P-type body region and the first N-type high voltage well are in contact with each other in the channel direction, wherein a portion of the second P-type body region is located vertically below the second gate, and wherein the second P-type body region and the second N-type high voltage well are in contact with each other in the channel direction;
a first N-type source and a first N-type drain, which are formed, by one same ion implantation process, in the semiconductor layer of the NMOS upper gate device region, wherein the first N-type source and the first N-type drain are located below and outside two sides of the first gate, respectively, wherein a side of the first gate which is closer to the first N-type source is a source side and another side of the first gate which is closer to the first N-type drain is a drain side, and wherein the first N-type source is located in the first P-type body region, and the first N-type drain is located in the first N-type high voltage well; and
a second N-type source and a second N-type drain, which are formed in the semiconductor layer of the NMOS lower gate device region by the one same ion implantation process that forms the first N-type source and the first N-type drain, wherein the second N-type source and the second N-type drain are located below and outside two sides of the second gate, respectively, wherein a side of the second gate which is closer to the second N-type source is a source side and another side of the second gate which is closer to the second N-type drain is a drain side, and wherein the second N-type source is located in the second P-type body region, and the second N-type drain is located in the second N-type high voltage well;
wherein the first N-type buried layer is formed in the semiconductor layer and in the substrate and is vertically below the first N-type high voltage well and the first P-type high voltage well;
wherein in the channel direction, the first N-type high voltage isolation region is in contact with a side of the first N-type high voltage well, wherein this side of the first N-type high voltage well is opposite to another side of the first N-type high voltage well which is in contact with the first P-type high voltage well;
wherein in the channel direction, the second N-type high voltage isolation region is in contact with a side of the first P-type high voltage well, wherein this side of the first P-type high voltage well is opposite to another side of the first P-type high voltage well which is in contact with the first N-type high voltage well.