US 12,408,369 B2
Vertical transport field effect transistors having different threshold voltages along the channel
Choonghyun Lee, Kanagawa (JP); Takashi Ando, Eastchester, NY (US); Alexander Reznicek, Troy, NY (US); and Jingyun Zhang, Albany, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Oct. 20, 2021, as Appl. No. 17/505,771.
Prior Publication US 2023/0124673 A1, Apr. 20, 2023
Int. Cl. H10D 30/63 (2025.01); H10D 30/01 (2025.01); H10D 62/17 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 62/822 (2025.01)
CPC H10D 30/63 (2025.01) [H10D 30/025 (2025.01); H10D 62/307 (2025.01); H10D 84/0167 (2025.01); H10D 84/0195 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 84/856 (2025.01); H10D 62/822 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A method comprising:
forming a vertical fin having a vertical channel, one end of the vertical channel comprising a doped layer and an opposite end comprising undoped silicon, the doped layer causing a threshold voltage at the one end to be different from a remainder of the vertical channel; and
forming a source and a drain each coupled to opposite ends of the vertical fin such that the drain is coupled to the undoped silicon, gate material being formed on the vertical channel, wherein the vertical fin comprises an intervening portion of undoped semiconductor material between the doped layer and the source.