| CPC H10D 30/6219 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6211 (2025.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/661 (2025.01); H10D 84/834 (2025.01)] | 15 Claims |
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1. A semiconductor device, comprising:
a semiconductor layer having a first portion defining a fin having a first height, a second portion at a first end of the fin in a first lateral direction, and a third portion at a second end of the fin in the first lateral direction, each of the second portion and the third portion having a second height lower than the first height;
a gate overlying the fin;
a source region comprising a first epitaxially grown semiconductor on the second portion of the semiconductor layer;
a drain region comprising a second epitaxially grown semiconductor on the third portion of the semiconductor layer, the source region and the drain region being at opposite ends of the gate in the first lateral direction; and
in cross-sectional view, a first sidewall spacer on one side of the gate and a second sidewall spacer on the opposite side of the gate, the first and second sidewall spacers directly contacting opposite sides of the gate on sides nearest to the gate and directly contacting the source region and the drain region, respectively, on sides farthest from the gate, wherein:
the fin has a lower portion below the second height and an upper portion above the second height, wherein the upper portion extends in the first lateral direction between the source region and the drain region;
the fin has a width in a second lateral direction perpendicular to the first lateral direction; and
each of the second and third portions of the semiconductor layer has a width in the second lateral direction.
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