| CPC H10D 30/475 (2025.01) [H10D 30/015 (2025.01); H10D 64/64 (2025.01)] | 8 Claims |
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1. A transistor comprising:
a semiconductor substrate having a top surface and a bottom surface;
a first current terminal;
a second current terminal;
a channel region formed at the top surface of the semiconductor substrate, the channel region comprising a semiconductor heterostructure configured to form a two-dimensional electron gas (2DEG) at a buried semiconductor heterojunction within the semiconductor heterostructure;
electrically-insulating material disposed on the top surface of the semiconductor substrate above the channel region;
an aperture in the electrically-insulating material between the first current terminal and the second current terminal, wherein the aperture is defined by an exposed portion of the top surface of the semiconductor substrate and straight vertical surfaces adjacent to the exposed portion, and the aperture has an aperture width equal to a distance between the vertical surfaces; and
an electrically-conductive control terminal that includes
a first metal layer directly on the exposed portion of the top surface of the semiconductor substrate above the channel region, wherein the first metal layer has a first thickness, the first metal layer extends between the vertical surfaces of the aperture, a width of the first metal layer equals the aperture width, and the first metal layer forms a Schottky contact to the channel region,
an intermediate metal layer disposed between the first metal layer and a metal gate electrode, wherein the intermediate metal layer has a first horizontal portion directly on the first metal layer, second vertical portions that directly contact the vertical surfaces of the aperture, and third horizontal portions that directly contact a top surface of the electrically-insulating material on both sides of the aperture, and wherein the first horizontal portion extends between the vertical surfaces of the aperture, and a width of the first horizontal portion equals the aperture width, and
the metal gate electrode disposed directly on the intermediate metal layer, wherein the metal gate electrode has a lower portion that extends into the aperture, and an upper portion directly on the lower portion, wherein the upper portion is wider than the aperture and extends over and directly contacts the third horizontal portions of the intermediate metal layer,
wherein the intermediate metal layer forms Ohmic contacts with each of the gate electrode and the first metal layer, and
wherein the intermediate metal layer is configured to impede atomic diffusion from the gate electrode toward the channel region.
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