US 12,408,361 B2
Silicide-block-ring body layout for non-integrated body LDMOS and LDMOS-based lateral IGBT
Zaichen Chen, Dallas, TX (US); and Akram Ali Salman, Plano, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,142.
Claims priority of provisional application 63/043,199, filed on Jun. 24, 2020.
Prior Publication US 2021/0408270 A1, Dec. 30, 2021
Int. Cl. H10D 12/00 (2025.01); H10D 12/01 (2025.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01)
CPC H10D 12/411 (2025.01) [H10D 12/01 (2025.01); H10D 30/65 (2025.01); H10D 62/127 (2025.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a semiconductor substrate having a doped region with a first conductivity type;
a source region located within the doped region, the source region having an opposite second conductivity type;
a drain region having the second conductivity type spaced apart from the source region; and
a gate electrode between the source region and the drain region, the gate electrode partially overlapping the doped region;
a heavily-doped body region having the first conductivity type located within the doped region and directly touching the source region; and
a first dielectric layer that forms a closed path around the body region and extends along a top surface of the source region and a top surface of the body region over a junction between the source region and the body region; and
a second dielectric layer that laterally abuts the first dielectric layer and is located on the top surface of the source region and the top surface of the body region.