US 12,408,358 B2
Semiconductor structure and formation method thereof
Jiancheng Hu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 13, 2022, as Appl. No. 17/647,900.
Application 17/647,900 is a continuation of application No. PCT/CN2021/100064, filed on Jun. 15, 2021.
Claims priority of application No. 202011047212.7 (CN), filed on Sep. 29, 2020.
Prior Publication US 2022/0140071 A1, May 5, 2022
Int. Cl. H10D 1/68 (2025.01); H10B 12/00 (2023.01)
CPC H10D 1/716 (2025.01) [H10B 12/033 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A semiconductor structure, wherein
the semiconductor structure comprises:
a base;
a plurality of lower electrodes located on the base, the lower electrode comprising a ring-like wall and a petal-like wall, the ring-like wall and the petal-like wall extending along a direction perpendicular to a surface of the base, and the petal-like wall dividing the ring-like wall internally into a plurality of discrete first openings;
a dielectric layer located on a bottom and a sidewall of the first opening; and
an upper electrode filling the first opening, the dielectric layer being located between the lower electrode and the upper electrode.