| CPC H10B 61/00 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 18 Claims |
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1. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate;
a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, wherein the uppermost interconnection lines protrude beyond the top surface of the lower insulating layer on the cell region;
data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region; and
an insulating spacer covering a side surface of each of the data storage patterns,
wherein the lower insulating layer on the cell region exposes side surfaces of the uppermost interconnection lines on the cell region, and
wherein the insulating spacer is adjacent to a corresponding one of the exposed side surfaces of the uppermost interconnection lines on the cell region.
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