| CPC H10B 53/20 (2023.02) | 19 Claims |
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1. A semiconductor device, comprising:
a first source layer spaced apart from a substrate and disposed in a memory cell region over the substrate;
a second source layer spaced apart from the substrate and disposed in a contact region over the substrate;
a cell stacked structure including interlayer insulating layers and conductive patterns alternately stacked on each other over the first source layer;
a discharge contact passing through at least a part of the second source layer; and
a dielectric layer disposed between the second source layer and the discharge contact,
wherein the second source layer is a first electrode of a capacitor and the discharge contact is a second electrode of the capacitor.
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