US 12,408,347 B2
Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines
Chih-Hsuan Cheng, Hsinchu (TW); Chieh-Fang Chen, Hsinchu County (TW); Sheng-Chen Wang, Hsinchu (TW); Chieh-Yi Shen, Taipei (TW); Han-Jong Chia, Hsinchu (TW); Feng-Ching Chu, Pingtung County (TW); Meng-Han Lin, Hsinchu (TW); Feng-Cheng Yang, Zhudong Township (TW); Yu-Ming Lin, Hsinchu (TW); and Chung-Te Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 9, 2022, as Appl. No. 17/667,873.
Claims priority of provisional application 63/224,113, filed on Jul. 21, 2021.
Prior Publication US 2023/0024339 A1, Jan. 26, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10B 51/10 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H10B 51/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor memory structure, comprising:
forming a stack over a substrate, the stack comprising first dielectric layers and second dielectric layers vertically alternately arranged;
forming first dielectric pillars through the stack;
etching the stack to form first trenches, wherein sidewalls of the first dielectric pillars are exposed from the first trenches;
removing the first dielectric pillars to form through holes;
removing the second dielectric layers of the stack to form gaps between the first dielectric layers; and
forming first conductive lines in the gaps.