US 12,408,346 B2
Semiconductor device and electronic system
Jaeryong Sim, Suwon-si (KR); Shinhwan Kang, Suwon-si (KR); and Jeehoon Han, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 1, 2024, as Appl. No. 18/760,980.
Application 18/760,980 is a continuation of application No. 17/204,248, filed on Mar. 17, 2021, granted, now 12,058,866.
Claims priority of application No. 10-2020-0100116 (KR), filed on Aug. 10, 2020.
Prior Publication US 2024/0357825 A1, Oct. 24, 2024
Int. Cl. H01L 29/792 (2006.01); H01L 23/48 (2006.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); H10B 43/27 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/50 (2023.02) [H01L 23/481 (2013.01); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a lower structure including a peripheral circuit;
a stack structure on the lower structure and including a first stack portion and a second stack portion, wherein the first stack portion includes first interlayer insulating layers and gate conductive layers alternately stacked in a vertical direction, and the second stack portion includes second interlayer insulating layers and third interlayer insulating layers alternately stacked in the vertical direction;
a vertical memory structure penetrating through the first stack portion in the vertical direction;
a capping insulating layer on the stack structure;
a peripheral contact plug penetrating through the capping insulating layer and the second stack portion in the vertical direction; and
gate contact plugs in contact with gate pads of the gate conductive layers,
wherein the first interlayer insulating layers and the second interlayer insulating layers include a first material,
wherein the third interlayer insulating layers include a second material different from the first material,
wherein the peripheral contact plug includes:
an upper plug portion penetrating the capping insulating layer and extending downward;
a lower plug portion at a lower level than a lowermost third interlayer insulating layer among the third interlayer insulating layers; and
an intermediate plug portion between the upper plug portion and the lower plug portion,
wherein the intermediate plug portion penetrates the lowermost third interlayer insulating layer and extends upward,
wherein the upper plug portion has a first upper side surface and a second upper side surface opposing each other in a first horizontal direction,
wherein the intermediate plug portion has a first intermediate side surface and a second intermediate side surface opposing each other in the first horizontal direction,
wherein a width of the upper plug portion is greater than a width of the intermediate plug portion,
wherein a side surface of the peripheral contact plug includes a bent portion extending from the first intermediate side surface of the intermediate plug portion toward the first upper side surface of the upper plug portion, and
wherein at least a portion of the bent portion of the side surface of the peripheral contact plug is at a lower level than an upper surface of an uppermost third interlayer insulating layer among the third interlayer insulating layers.
 
18. An electronic system, comprising:
a main substrate;
a semiconductor device on the main substrate; and
a controller electrically connected to the semiconductor device,
wherein the semiconductor device includes:
a lower structure including a peripheral circuit;
a stack structure on the lower structure and including a first stack portion and a second stack portion, wherein the first stack portion includes first interlayer insulating layers and gate conductive layers alternately stacked in a vertical direction, and wherein the second stack portion includes second interlayer insulating layers and third interlayer insulating layers alternately stacked in the vertical direction;
a vertical memory structure penetrating through the first stack portion in the vertical direction;
a capping insulating layer on the stack structure;
a peripheral contact plug penetrating through the capping insulating layer and the second stack portion in the vertical direction; and
gate contact plugs in contact with gate pads of the gate conductive layers,
wherein the first interlayer insulating layers and the second interlayer insulating layers include a first material,
wherein the third interlayer insulating layers include a second material different from the first material,
wherein the peripheral contact plug includes:
an upper plug portion penetrating the capping insulating layer and extending downward;
a lower plug portion at a lower level than a lowermost third interlayer insulating layer among the third interlayer insulating layers; and
an intermediate plug portion between the upper plug portion and the lower plug portion,
wherein the intermediate plug portion penetrates the lowermost third interlayer insulating layer and extends upward,
wherein the upper plug portion has a first upper side surface and a second upper side surface opposing each other in a first horizontal direction,
wherein the intermediate plug portion has a first intermediate side surface and a second intermediate side surface opposing each other in the first horizontal direction,
wherein a width of the upper plug portion is greater than a width of the intermediate plug portion,
wherein a side surface of the peripheral contact plug includes a bent portion extending from the first intermediate side surface of the intermediate plug portion toward the first upper side surface of the upper plug portion, and
wherein at least a portion of the bent portion of the side surface of the peripheral contact plug is at a lower level than an upper surface of an uppermost third interlayer insulating layer among the third interlayer insulating layers.