US 12,408,344 B2
Semiconductor memory device
Hisashi Harada, Yokkaichi (JP); and Keisuke Suda, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 13, 2022, as Appl. No. 17/931,621.
Claims priority of application No. 2022-022291 (JP), filed on Feb. 16, 2022.
Prior Publication US 2023/0262983 A1, Aug. 17, 2023
Int. Cl. H10B 43/35 (2023.01); G11C 5/06 (2006.01); H10B 43/20 (2023.01)
CPC H10B 43/35 (2023.02) [G11C 5/063 (2013.01); H10B 43/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a source layer arranged above a substrate in a first direction;
a first interconnect layer arranged between the substrate and the source layer;
a second interconnect layer arranged between the substrate and the source layer and arranged adjacent to the first interconnect layer in a second direction intersecting the first direction;
a plurality of memory pillars penetrating through the first interconnect layer in the first direction, and each having a semiconductor film which extends in the first direction and is electrically coupled to the source layer at an end portion in the first direction; and
a first member provided between the first interconnect layer and the second interconnect layer in the second direction, an end portion in the first direction of the first member being in contact with the source layer,
wherein the source layer has a first semiconductor layer which is in contact with the semiconductor film of each of the memory pillars and a second semiconductor layer which is arranged between the substrate and the first semiconductor layer,
in the first semiconductor layer, a surface on an opposite side to the substrate in the first direction has at least one first projecting portion projecting in the first direction and overlapping a part of an area in the first direction, the area being provided with the first interconnect layer and the first member, and
in the second semiconductor layer, a surface on an opposite side to the substrate in the first direction is in contact with the first semiconductor layer without having a projecting portion projecting in the first direction.