US 12,408,343 B2
Semiconductor memory device and manufacturing method of semiconductor memory device
Ga Ram Choi, Icheon-si (KR); Dae Hyun Kim, Icheon-si (KR); and Changhan Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 2, 2022, as Appl. No. 18/073,908.
Claims priority of application No. 10-2022-0082182 (KR), filed on Jul. 5, 2022.
Prior Publication US 2024/0015965 A1, Jan. 11, 2024
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 51/20 (2023.01); H10B 63/00 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 51/20 (2023.02); H10B 63/34 (2023.02)] 36 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a first doped semiconductor layer and a second doped semiconductor layer each comprising an upper surface facing a first direction, the first and second doped semiconductor layers spaced apart from each other;
a multifunctional stack including a plurality of first interlayer insulating layers and a plurality of first conductive layers stacked alternately with each other in the first direction above the first doped semiconductor layer, the multifunctional stack including a groove;
a liner insulating layer on a bottom surface of the groove;
a liner semiconductor layer on the liner insulating layer;
a first electrode located in the grove and extending in the first direction from the liner semiconductor layer;
a second electrode located in the grove and extending in the first direction from the liner semiconductor layer, wherein the first electrode and the second electrode are spaced apart from each other;
a gate stack including a plurality of second interlayer insulating layers and a plurality of second conductive layers stacked alternately with each other in the first direction on the second doped semiconductor layer, the gate stack including a vertical hole;
a memory layer on a side portion of the vertical hole; and
a vertical semiconductor layer arranged on the memory layer.