US 12,408,342 B2
Memory device with multi-layered charge storage stack
Chi-Pin Lu, Zhubei (TW); Pei-Ci Jhang, Zhudong Township, Hsinchu County (TW); Masaru Nakamichi, Chigasaki (JP); Ling-Wuu Yang, Hsinchu (TW); and Kuang-Chao Chen, Taipei (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Jun. 10, 2022, as Appl. No. 17/837,227.
Prior Publication US 2023/0403852 A1, Dec. 14, 2023
Int. Cl. H10B 43/27 (2023.01)
CPC H10B 43/27 (2023.02) 10 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a plurality of gate layers laterally extending above a substrate and spaced apart from each other;
a laterally stacked multi-layered memory structure extending upwardly above the substrate and through the gate layers and comprising:
a blocking layer;
a charge storage stack on the blocking layer and comprising a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers, wherein the first silicon nitride layer and the second nitride layer are symmetrically arranged with respect to the silicon oxynitride layer, and have substantially the same thickness; and
a tunneling layer on the charge storage stack; and
a vertical channel layer on the laterally stacked multi-layered memory structure.