US 12,408,341 B2
Memory arrays, and methods of forming memory arrays
Changhan Kim, Boise, ID (US); Chet E. Carter, Boise, ID (US); Cole Smith, Boise, ID (US); Collin Howder, Meridian, ID (US); Richard J. Hill, Boise, ID (US); and Jie Li, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 10, 2022, as Appl. No. 17/692,004.
Application 16/674,823 is a division of application No. 15/948,639, filed on Apr. 9, 2018, granted, now 10,497,715, issued on Dec. 3, 2019.
Application 17/692,004 is a continuation of application No. 16/674,823, filed on Nov. 5, 2019, granted, now 11,302,708.
Claims priority of provisional application 62/610,657, filed on Dec. 27, 2017.
Prior Publication US 2022/0199645 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/41 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10D 30/01 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01); H10D 64/68 (2025.01)
CPC H10B 43/27 (2023.02) [H01L 21/0214 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/0223 (2013.01); H01L 21/02636 (2013.01); H01L 21/31111 (2013.01); H01L 23/528 (2013.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/41 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/683 (2025.01); H10D 30/689 (2025.01); H10D 30/693 (2025.01); H10D 62/292 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01); H10D 64/679 (2025.01); H10D 64/685 (2025.01); H10D 64/693 (2025.01); H01L 21/02255 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An assembly, comprising:
a channel region including a first channel portion and a second channel portion under the first channel portion;
a tunneling material extending along an entirety of the channel region;
a first memory cell structure located between a first gate and the first channel portion; the first memory cell structure including a first charge-storage region and a first charge-blocking region; the first charge-blocking region being located between the first charge-storage region and the first gate;
a second memory cell structure under the first memory cell structure and located between a second gate and the second channel portion; the second memory cell structure including a second charge-storage region and a second charge-blocking region; the second charge-blocking region being located between the second charge-storage region and the second gate;
a void between the first and second gates, and between the first and second memory cell structures and extending to the tunneling material;
a first liner between the silicon nitride of the first charge-storage region and the void;
a second liner between the silicon nitride of the second charge-storage region and the void;
a first dielectric barrier region being between the first gate and the first charge-blocking region, the first dielectric barrier region being directly against the void along a lower surface of the first charge-blocking region;
a second dielectric barrier region being between the second gate and the second charge-blocking region, the second dielectric barrier region being directly against the void along an upper surface of the second charge-blocking region;
a first region of a low-density silicon dioxide between the first gate and the void;
a second region of the low-density silicon dioxide between the second gate and the void;
an insulative material along and directly contacting a portion of the first region of low-density silicon dioxide and along and directly contacting a portion of the second regions of low-density silicon dioxide, the insulative material comprising silicon dioxide having a higher density than the low-density silicon dioxide of the first and second regions; and
wherein an edge of the first dielectric barrier region is directly against the void; and wherein an edge of the second dielectric barrier region is directly against the void, and wherein the first region of low-density silicon dioxide does not contact the second region of low-density silicon dioxide.