US 12,408,339 B2
Memory devices having vertical transistors and methods for forming the same
Hongbin Zhu, Wuhan (CN); Wei Liu, Wuhan (CN); and Yanhong Wang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 16, 2021, as Appl. No. 17/553,772.
Application 17/553,772 is a continuation of application No. PCT/CN2021/115704, filed on Aug. 31, 2021.
Prior Publication US 2023/0066312 A1, Mar. 2, 2023
Int. Cl. H10B 41/40 (2023.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10D 30/67 (2025.01)
CPC H10B 41/40 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10D 30/6735 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor,
wherein the vertical transistor comprises a semiconductor body extending in the first direction and a gate structure in contact with a plurality of sides of the semiconductor body, and one end of the semiconductor body coupled to the storage unit is flush with a gate electrode of the gate structure in a plane perpendicular to the first direction, at a first side of the second semiconductor structure, electrodes of part of the storage units being connected to extend in a second direction perpendicular to the first direction; and
a plurality of bit lines coupled to the vertical transistors of the memory cells and each extending in the second direction, wherein a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the vertical transistors in the first direction, the vertical transistors being arranged between the bit lines and the storage units; and
at a second side of the second semiconductor structure opposite the first side, a bonding interface arranged between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface.