US 12,408,338 B2
Memory devices having vertical transistors and methods for forming the same
Hongbin Zhu, Wuhan (CN); Wei Liu, Wuhan (CN); and Yanhong Wang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 16, 2021, as Appl. No. 17/553,763.
Application 17/553,763 is a continuation of application No. PCT/CN2021/115545, filed on Aug. 31, 2021.
Prior Publication US 2023/0062083 A1, Mar. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/40 (2023.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/40 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising a first array of memory cells;
a third semiconductor structure comprising a second array of memory cells, wherein each of the memory cells of the first and second arrays comprises a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor;
a first bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the first array of memory cells is coupled to the peripheral circuit across the first bonding interface; and
a second bonding interface between the second semiconductor structure and the third semiconductor structure in the first direction, wherein the second array of memory cells is coupled to the peripheral circuit across the first bonding interface and the second bonding interfaces,
wherein:
the peripheral circuit is configured to send a first signal to a first word line of the first array of memory cells in the second semiconductor structure through the first bonding interface; and
the peripheral circuit is configured to send a second signal to a second word line of the second array of memory cells in the third semiconductor structure through the first bonding interface, the second bonding interface, and a contact that extends through the second semiconductor structure.