| CPC H10B 41/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 10 Claims |

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1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers, wherein the electrically conductive layers comprise word lines and drain select gate electrodes that comprise plurality of drain-select-level electrically conductive strips which are located above the word lines memory stack structures vertically extending through the alternating stack;
drain-select-level isolation structures located between a respective neighboring pair of drain-select-level electrically conductive strips; and
a first laterally-insulated contact via assembly comprising a first layer contact via structure and a first tubular insulating spacer,
wherein:
the first laterally-insulated contact via assembly contacts a top surface of a first word line of the word lines;
the first laterally-insulated contact via assembly laterally contacts a first drain-select-level isolation structure of the drain-select-level isolation structures; and
the first drain-select-level isolation structure laterally extends through the entirety of the first laterally-insulated contact via assembly, and is in direct contact with two planar vertical sidewall segments of the first tubular insulating spacer and with two planar vertical sidewall segments of the first layer contact via structure.
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