	US 12,408,334 B2
	Method for manufacturing fully self-aligned high-density 3D multi-layer memory
Jack Zezhong Peng, Chengdu (CN); and Ke Wang, Chengdu (CN)
Assigned to CHENGDU PBM TECHNOLOGY LTD., Chengdu (CN)
Appl. No. 17/799,880
Filed by CHENGDU PBM TECHNOLOGY LTD., Chengdu (CN)
PCT Filed Sep. 30, 2021, PCT No. PCT/CN2021/122090 § 371(c)(1), (2) Date Aug. 15, 2022, PCT Pub. No. WO2022/174593, PCT Pub. Date Aug. 25, 2022.
Claims priority of application No. 202110189418.1 (CN), filed on Feb. 19, 2021.
Prior Publication US 2023/0345714 A1, Oct. 26, 2023
Int. Cl. H01L 21/31 (2006.01); H01L 21/311 (2006.01); H10B 20/00 (2023.01); H10D 8/01 (2025.01)

CPC H10B 20/40 (2023.02) [H01L 21/311 (2013.01); H10D 8/051 (2025.01)]

9 Claims

1. A method for manufacturing a fully self-aligned high-density three-dimensional (3D) multi-layer memory, comprising:

step 1: forming a base structure, wherein a predetermined number of conductive medium layers and a predetermined number of insulating medium layers are disposed in such a manner that the conductive medium layers and the insulating medium layers are alternately stacked on each other, to form the base structure; and

step 2: grooving the base structure, wherein the base structure is grooved to form a curved division groove penetrating from a top layer to a bottom layer in the base structure, so that the division groove divides the base structure into two interdigitated structures that are staggered and separated from each other;

step 3: filling an insulating medium in the division groove;

step 4: deep-hole etching the insulating medium in step 3 to form memory cell holes discretely arranged along the division groove, wherein the insulating medium is present between adjacent memory cell holes, and the conductive medium layers and the insulating medium layers of the base structure are exposed at the inner walls of the memory cell holes; and

step 5: disposing various layers of medium required by a preset memory structure layer by layer onto inner walls of the memory cell holes, comprising:

step 5.1: depositing an intermediate medium layer on the inner wall of each memory cell hole step 5.2: etching the intermediate medium layer in a bottom area of the memory cell hole, to form a through hole penetrating through the intermediate medium layer; and

step 5.3: disposing a core medium layer in the memory cell hole; wherein

materials of the conductive medium layer, the intermediate medium layer, and the core medium layer are one of the following:

(a) the conductive medium layer is a P-type semiconductor, the intermediate medium layer is an insulating material, and the core medium layer is an N-type semiconductor;

(b) the conductive medium layer is the N-type semiconductor, the intermediate medium layer is the insulating material, and the core medium layer is the P-type semiconductor;

(c) the conductive medium layer is Schottky metal, the intermediate medium layer is the insulating material, and the core medium layer is a semiconductor; and

(d) the conductive medium layer is the semiconductor, the intermediate medium layer is the insulating material, and the core medium layer is the Schottky metal.