US 12,408,332 B2
Memory devices having one-time-programmable fuses and/or antifuses formed from thin-film transistors
Paolo Fantini, Vimercate (IT); Lorenzo Fratin, Milan (IT); and Fabio Pellizzer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 29, 2022, as Appl. No. 17/898,232.
Prior Publication US 2024/0074168 A1, Feb. 29, 2024
Int. Cl. H10B 20/25 (2023.01)
CPC H10B 20/25 (2023.02) 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate;
an insulative layer over the substrate;
a memory array over the insulative layer; and
a plurality of transistors positioned in the insulative layer, wherein the transistors each include a source, a drain, and a gate, and wherein the transistors are configured as fuses such that (a) the transistors in a first subset of the transistors have a first resistance across the gate and (b) the transistors in a second subset of the transistors have a second resistance across the gate that is greater than the first resistance.